A bus architecture of a computer system conveys much of the information and signals involved in the computer system's operation. In a typical computer system, one or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. With many peripheral devices, such as graphics adapters, full motion video adapters, small computer systems interface (SICS) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems that benefit substantially from a very fast bus transfer rate.
Much of a computer system's functionality and usefulness to a user is derived from the functionality of the peripheral devices. For example, the speed and responsiveness of the graphics adapter is a major factor in a computer system's usefulness as an entertainment device. Or, for example, the speed with which video files can be retrieved from a hard drive and played by the graphics adapter determines the computer system's usefulness as a training aid. Hence, the rate at which data can be transferred among the various peripheral devices often determines whether the computer system is suited for a particular purpose. The electronics industry has, over time, developed several types of bus architectures. Recently, the PCI (peripheral component interconnect) bus architecture has become one of the most widely used, widely supported bus architectures in the industry. The PCI bus was developed to provide a high speed, low latency bus architecture from which a large variety of systems could be developed.
Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102 and a main memory 104, coupled to a host PCI bridge containing arbiter 106 (hereafter arbiter 106) through a CPU local bus 108 and memory bus 110, respectively. A PCI bus 112 is coupled to each of PCI agents 114, 116, 118, 120, 122, 124 respectively, and is coupled to arbiter 106.
Referring still to Prior Art FIG. 1, each of PCI agents 114, 116, 118, 120, 122, 124 (hereafter, PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, for example, interface control lines, address/data lines, error signal lines, and the like. Each of PCI agents 114-124 are coupled to the functional signal lines comprising PCI bus 112. When one of PCI agents 114-124 requires the use of PCI bus 112 to transmit data, it requests PCI bus ownership from arbiter 106. The PCI agent requesting ownership is referred to as an "initiator", or bus master. Upon being granted ownership of PCI bus 112 from arbiter 106, the initiator (e.g., PCI agent 116) carries out its respective data transfer.
Each of PCI agents 114-124 may independently request PCI bus ownership. Thus, at any given time, several of PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent is granted PCI bus ownership. When one of PCI agents 114-124 is granted PCI bus ownership, it initiates it transaction (e.g., data transfer) with a "target " or slave device (e.g., main memory 104). When the data transaction is complete, the PCI agent relinquishes ownership of the PCI bus, allowing arbiter 106 to reassign PCI bus 112 to another requesting PCI agent.
Thus, only one data transaction can take place on a PCI bus at any given time. In order to maximize the efficiency and data transfer bandwidth of PCI bus 112, PCI agents 114-124 follow a definitive set of protocols and rules. These protocols are designed to standardize the method of accessing, utilizing, and relinquishing PCI bus 112, so as to maximize its data transfer bandwidth. The PCI bus protocols and specifications are set forth in an industry standard PCI specification (e.g., PCI Specification--Revision 2.1). Where each of PCI agents 114-124 are high performance, well designed devices, data transfer rates of up to 528 Mbytes per second can be achieved (e.g., PCI bus 112 operating at 66 MHz).
Prior art FIG. 2 shows a diagram of arbiter 106, PCI bus 112, PCI target 114, and PCI target 116 in greater detail. As depicted in FIG. 2, PCI bus 112 is a 64-bit PCI bus (in accordance with PCI specification--Revision 2.1). However, PCI bus 112 hosts a mixed 32-bit and 64-bit PCI environment. PCI target 114 is a 64-bit PCI device, while PCI target 116 is a 32-bit PCI device. In accordance with the PCI specification, a 64-bit PCI bus (e.g., 64-bit PCI bus 112) must be fully functional and adequately host both 32-bit and 64-bit PCI devices. With both 32-bit and 64-bit devices coupled to a common 64-bit PCI bus (e.g., 64-bit PCI bus 112), a 64-bit PCI initiator, when it starts a cycle, is required to determine the width of the target (e.g., whether the target device is a 32-bit or 64-bit device), by asserting the REQ64# signal and waiting for the ACK64# signal being asserted with DEVSEL# by the target device. If the target device asserts ACK64# with DEVSEL#, then the target device is notifying the initiator that it is a 64-bit device. If ACK64# is not asserted with DEVSEL#, then the 64-bit initiator determines that the target device is a 32-bit device.
Thus, once the 64-bit PCI initiator 106 determines that the target device 116 is a 32-bit PCI target, the 64-bit PCI initiator 106 performs "data-steering" to transfer the data from its data transaction 32-bits at a time. However, there exists a problem in the fact that single data transaction 64-bit transfers are very inefficient using this scheme.
As is well known, using a single data phase with 64-bit transfers may not be very effective. Since the 64-bit PCI initiator 106 does not know how the transaction will be resolved with ACK64# until DEVSEL# is returned, it does not know the clock on which to deasseirt FRAME# for a 64-bit single dataphase transaction. IRDY# must remain deasserted, until FRAMES signaling is resolved. The single 64-bit data phase may have to be split into two 32-bit data phases when the target is only 32-bits, which means a two phase 32-bit transfer is a least as fast as a one phase 64-bit transfer.
Prior art FIG. 3 shows a timing diagram 300 of 64-bit PCI initiator 106 transferring a 64-bit data, using the REQ64#, ACK64# protocol, to 64-bit PCI target 114. The left side of timing diagram 300 shows the standard signals of 64-bit PCI bus 112. The letter "Z" signifies that the relevant signal lines are tri-stated. As shown by arrows 301, it should be noted that until ACK64# is sampled asserted by 64-bit PCI initiator 106, FRAME# cannot be deasserted and IRDY# cannot be asserted, which causes a 3-clock cycle data transfer transaction, when there is only one 64-bit data to transfer.
Prior art FIG. 4 shows a timing diagram 400 of 64-bit PCI initiator 106 transferring a 64-bit data, using the REQ64#, ACK64# protocol, to a 32-bit PCI target 116. Diagram 400 shows a case where 64-bit PCI initiator 106 transfers a 64-bit data to 32-bit PCI target 116. As shown in diagram 400, when 64-bit PCI initiator 106 samples that the ACK64# is not asserted with DEVSEL#, the initiator knows that the target is a 32-bit target and that it has to burst the 64-bit data as two 32-bit data transfers. This is shown by the assertion of FRAME# with IRDY#. ACK64# is never asserted by 32-bit PCI target 116. This causes a four clock cycle data transfer transaction to transfer a 64-bit data to a 32-bit target through the REQ64#, ACK64# protocol.
Thus, what is required is a more efficient solution for transferring 64-bit data in a mixed 64-bit/32-bit PCI environment. What is required is a solution which allows more efficient transfers of 64-bit data from a 64bit PCI initiator device to a 64-bit target device in a mixed 64-bit/32-bit PCI environment. Additionally, what is further required is a solution which allows more efficient transfers from a 64-bit initiator device to a 32-bit target device in a mixed 64-bit/32-bit PCI environment.